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LHF64P01
* Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. * When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * Office electronics * Instrumentation and measuring equipment * Machine tools * Audiovisual equipment * Home appliance * Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trains, automobiles, and other transportation equipment * Mainframe computers * Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment * Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * Aerospace equipment * Communications equipment for trunk lines * Control equipment for the nuclear power industry * Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. * Please direct all queries regarding the products covered herein to a sales representative of the company.
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CONTENTS
PAGE 56-Lead TSOP (Normal Bend) Pinout ....................... 3 Pin Descriptions.......................................................... 4 CE0, CE1, CE2 Truth Table ....................................... 5 Memory Map .............................................................. 6 Identifier Codes Address ............................................ 7 OTP Block Address Map............................................ 8 Bus Operation............................................................. 9 Command Definitions .............................................. 10
PAGE 1 Electrical Specifications ........................................ 16 1.1 Absolute Maximum Ratings........................... 16 1.2 Operating Conditions ..................................... 16 1.2.1 Capacitance.............................................. 17 1.2.2 AC Input/Output Test Conditions............ 17 1.2.3 DC Characteristics................................... 18 1.2.4 AC Characteristics Read-Only Operations .............................. 20 1.2.5 AC Characteristics - Write Operations.... 24
Functions of Block Lock .......................................... 12 1.2.6 Reset Operations...................................... 26 Status Register Definition......................................... 13 Extended Status Register Definition ........................ 14 STS Configuration Definition .................................. 15 2 Related Document Information ............................. 28 3 Package and packing specification........................ 29 1.2.7 Block Erase, (Page Buffer) Program and Block Lock Configuration Performance.............................................. 27
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LH28F640SPHT-PTL12 64Mbit (4Mbitx16/8Mbitx8) Page Mode Flash MEMORY
64-Mbit Density * Bit Organization x8/x16 High Performance Page Mode Reads for Memory Array * 120/25ns 4-Word/ 8-Byte Page Mode VCC=2.7V-3.6V Operation * VCCQ for Input/Output Power Supply Isolation * Automatic Power Savings Mode reduces ICCR in Static Mode OTP (One Time Program) Block * 4-Word/ 8-Byte Factory-Programmed Area * 3963-Word/ 7926-Byte User-Programmable Area High Performance Program with Page Buffer * 16-Word/ 32-Byte Page Buffer * Page Buffer Program Time 12.5s/byte (Typ.) Operating Temperature -40C to +85C Symmetrically-Blocked Architecture * Sixty-four 64-KWord/ 128-KByte Blocks Enhanced Data Protection Features * Individual Block Lock * Absolute Protection with VPENVPENLK * Block Erase, (Page Buffer) Program Lockout during Power Transitions Automated Erase/Program Algorithms * Program Time 210s (Typ.) * Block Erase Time 1s (Typ.) Cross-Compatible Command Support * Basic Command Set * Common Flash Interface (CFI) Extended Cycling Capability * Minimum 100,000 Block Erase Cycles 56-Lead TSOP (Normal Bend) CMOS Process (P-type silicon substrate) ETOXTM* Flash Technology Not designed or rated as radiation hardened
The product, which is Page Mode Flash memory, is a high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can operate at VCC=2.7V-3.6V and VPEN=2.7V-3.6V The product supports high performance page mode. It allows code execution directly from Flash, thus eliminating time consuming wait states. Fast program capability is provided through the use of high speed Page Buffer Program. The block locking scheme is available for memory array and this scheme provides maximum flexibility for safe nonvolatile code and data storage. OTP (One Time Program) block provides an area to store security code and to protect its code. * ETOX is a trademark of Intel Corporation.
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A22 CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56-LEAD TSOP STANDARD PINOUT 14mm x 20mm TOP VIEW
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
NC WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2
Figure 1. 56-Lead TSOP (Normal Bend) Pinout
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Table 1. Pin Descriptions Symbol A0 A22-A1 Type INPUT Name and Function ADDRESS INPUTS: Lowest address input in byte mode (BYTE#=VIL : x8 bit). Address is internally latched during an erase or a program cycle. This pin is not used in word mode (BYTE#=VIH : x16 bit) ADDRESS INPUTS: Inputs for addresses during read, erase and program operations. Addresses are internally latched during an erase or a program cycle. DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code, identifier code reads. Data pins float to high-impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle. DQ15-DQ8 pins are not used in byte mode (BYTE#=VIL : x8 bit). CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. When the device is de-selected, power consumption reduces to standby levels. Refer to Table 2 to determine whether the device is selected or de-selected depending on the state of CE0, CE1 and CE2. RESET: When low (VIL), RP# resets internal automation and inhibits erase and program operations, which provides data protection. RP#-high (VIH) enables normal operation. After power-up or reset mode, the device is automatically set to read array mode. RP# must be low during power-up/down. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the first edge of CE0, CE1 or CE2 that disables the device or the rising edge of WE# (whichever occurs first).
INPUT
DQ15-DQ0
INPUT/ OUTPUT
CE0, CE1, CE2
INPUT
RP#
INPUT
OE# WE#
INPUT INPUT
STS
STATUS: Indicates the status of the internal WSM (Write State Machine). When configured in level mode (default mode), STS acts as a RY/BY# pin (STS is VOL when OPEN DRAIN the WSM is executing internal erase or program algorithms). When configured in one of OUTPUT its pulse modes, STS can pulse to indicate erase/program completion. Refer to Table 9 for STS configuration. INPUT BYTE ENABLE: BYTE# VIL places the device in byte mode (x8). In this mode, DQ15DQ8 is floated (High Z) and A0 is the lowest address input. BYTE# VIH places the device in word mode (x16) and A1 is the lowest address input. MONITORING POWER SUPPLY VOLTAGE: VPEN is not used for power supply pin. With VPENVPENLK, block erase, (page buffer) program, block lock configuration and OTP program cannot be executed and should not be attempted. DEVICE POWER SUPPLY (2.7V-3.6V): With VCCVLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (refer to DC Characteristics) produce spurious results and should not be attempted. INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output pins. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated.
BYTE#
VPEN
INPUT
VCC VCCQ GND NC
SUPPLY
SUPPLY SUPPLY
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Table 2. CE0, CE1, CE2 Truth Table (1) CE2 VIL VIL VIL VIL VIH VIH VIH VIH CE1 VIL VIL VIH VIH VIL VIL VIH VIH CE0 VIL VIH VIL VIH VIL VIH VIL VIH Device Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTE: 1. For single-chip applications, CE1 and CE2 can be connected to GND.
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[A22-A1]
3FFFFF 3F0000 3EFFFF 3E0000 3DFFFF 3D0000 3CFFFF 3C0000 3BFFFF 3B0000 3AFFFF 3A0000 39FFFF 390000 38FFFF 380000 37FFFF 370000 36FFFF 360000 35FFFF 350000 34FFFF 340000 33FFFF 330000 32FFFF 320000 31FFFF 310000 30FFFF 300000 2FFFFF 2F0000 2EFFFF 2E0000 2DFFFF 2D0000 2CFFFF 2C0000 2BFFFF 2B0000 2AFFFF 2A0000 29FFFF 290000 28FFFF 280000 27FFFF 270000 26FFFF 260000 25FFFF 250000 24FFFF 240000 23FFFF 230000 22FFFF 220000 21FFFF 210000 20FFFF 200000
[A22-A0]
64-Kword/128-Kbyte Block 63 64-Kword/128-Kbyte Block 62 64-Kword/128-Kbyte Block 61 64-Kword/128-Kbyte Block 60 64-Kword/128-Kbyte Block 59 64-Kword/128-Kbyte Block 58 64-Kword/128-Kbyte Block 57 64-Kword/128-Kbyte Block 56 64-Kword/128-Kbyte Block 55 64-Kword/128-Kbyte Block 54 64-Kword/128-Kbyte Block 53 64-Kword/128-Kbyte Block 52 64-Kword/128-Kbyte Block 51 64-Kword/128-Kbyte Block 50 64-Kword/128-Kbyte Block 49 64-Kword/128-Kbyte Block 48 64-Kword/128-Kbyte Block 47 64-Kword/128-Kbyte Block 46 64-Kword/128-Kbyte Block 45 64-Kword/128-Kbyte Block 44 64-Kword/128-Kbyte Block 43 64-Kword/128-Kbyte Block 42 64-Kword/128-Kbyte Block 41 64-Kword/128-Kbyte Block 40 64-Kword/128-Kbyte Block 39 64-Kword/128-Kbyte Block 38 64-Kword/128-Kbyte Block 37 64-Kword/128-Kbyte Block 36 64-Kword/128-Kbyte Block 35 64-Kword/128-Kbyte Block 34 64-Kword/128-Kbyte Block 33 64-Kword/128-Kbyte Block 32
7FFFFF 7E0000 7DFFFF 7C0000 7BFFFF 7A0000 79FFFF 780000 77FFFF 760000 75FFFF 740000 73FFFF 720000 71FFFF 700000 6FFFFF 6E0000 6DFFFF 6C0000 6BFFFF 6A0000 69FFFF 680000 67FFFF 660000 65FFFF 640000 63FFFF 620000 61FFFF 600000 5FFFFF 5E0000 5DFFFF 5C0000 5BFFFF 5A0000 59FFFF 580000 57FFFF 560000 55FFFF 540000 53FFFF 520000 51FFFF 500000 4FFFFF 4E0000 4DFFFF 4C0000 4BFFFF 4A0000 49FFFF 480000 47FFFF 460000 45FFFF 440000 43FFFF 420000 41FFFF 400000
[A22-A1]
1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
[A22-A0]
64-Kword/128-Kbyte Block 31 64-Kword/128-Kbyte Block 30 64-Kword/128-Kbyte Block 29 64-Kword/128-Kbyte Block 28 64-Kword/128-Kbyte Block 27 64-Kword/128-Kbyte Block 26 64-Kword/128-Kbyte Block 25 64-Kword/128-Kbyte Block 24 64-Kword/128-Kbyte Block 23 64-Kword/128-Kbyte Block 22 64-Kword/128-Kbyte Block 21 64-Kword/128-Kbyte Block 20 64-Kword/128-Kbyte Block 19 64-Kword/128-Kbyte Block 18 64-Kword/128-Kbyte Block 17 64-Kword/128-Kbyte Block 16 64-Kword/128-Kbyte Block 15 64-Kword/128-Kbyte Block 14 64-Kword/128-Kbyte Block 13 64-Kword/128-Kbyte Block 12 64-Kword/128-Kbyte Block 11 64-Kword/128-Kbyte Block 10 64-Kword/128-Kbyte Block 9 64-Kword/128-Kbyte Block 8 64-Kword/128-Kbyte Block 7 64-Kword/128-Kbyte Block 6 64-Kword/128-Kbyte Block 5 64-Kword/128-Kbyte Block 4 64-Kword/128-Kbyte Block 3 64-Kword/128-Kbyte Block 2 64-Kword/128-Kbyte Block 1 64-Kword/128-Kbyte Block 0
3FFFFF 3E0000 3DFFFF 3C0000 3BFFFF 3A0000 39FFFF 380000 37FFFF 360000 35FFFF 340000 33FFFF 320000 31FFFF 300000 2FFFFF 2E0000 2DFFFF 2C0000 2BFFFF 2A0000 29FFFF 280000 27FFFF 260000 25FFFF 240000 23FFFF 220000 21FFFF 200000 1FFFFF 1E0000 1DFFFF 1C0000 1BFFFF 1A0000 19FFFF 180000 17FFFF 160000 15FFFF 140000 13FFFF 120000 11FFFF 100000 0FFFFF 0E0000 0DFFFF 0C0000 0BFFFF 0A0000 09FFFF 080000 07FFFF 060000 05FFFF 040000 03FFFF 020000 01FFFF 000000
Figure 2. Memory Map
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Table 3. Identifier Codes Address Code Manufacturer Code Device Code Block Lock Configuration Code Manufacturer Code Device Code Block is Unlocked Block is Locked Address [A22-A1] (1) 000000H 000001H Block Address +2 Data [DQ7-DQ0] B0H 17H DQ0 = 0 DQ0 = 1 Notes 2 2 3 3
NOTES: 1. The address A0 don't care. 2. "00H" is presented on DQ15-DQ8 in word mode (BYTE#=VIH : x16 bit). 3. Block Address = The beginning location of a block address. DQ15-DQ1 are reserved for future implementation.
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[A22-A1] 000FFFH Customer Programmable Area 000085H 000084H 000081H 000080H Factory Programmed Area
Reserved for Future Implementation (DQ15-DQ2)
[A22-A0] 001FFFH
00010AH 000109H 000102H 000100H
Customer Programmable Area Lock Bit (DQ1) Factory Programmed Area Lock Bit (DQ0)
Figure 3. OTP Block Address Map (The area not specified in the above figure cannot be used.)
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Table 4. Bus Operation(1, 2) Mode Read Array Output Disable Standby Reset Read Identifier Codes/OTP Read Query Write 5 8 8,9 6,7,8 Notes 8 RP# VIH VIH VIH VIL VIH VIH VIH CE0,1,2 (3) Enabled Enabled Disabled X Enabled Enabled Enabled OE# VIL VIH X X VIL VIL VIH WE# VIH VIH X X VIH VIH VIL Address X X X X Refer to Table 3 See Appendix X VPEN X X X X X X X DQ (4) DOUT High Z High Z High Z Refer to Table 3 See Appendix DIN STS (10) X X X High Z X X X
NOTES: 1. Refer to DC Characteristics. When VPENVPENLK, memory contents can be read, but cannot be altered. 2. X can be VIL or VIH for control pins and addresses, and VPENLK or VPENH for VPEN. Refer to DC Characteristics for VPENLK and VPENH voltages. 3. Refer to Table 2 to determine whether the device is selected or de-selected depending on the state of CE0, CE1 and CE2. 4. DQ refers to DQ15-DQ0 in word mode (BYTE#=VIH : x16 bit) and DQ7-DQ0 in byte mode (BYTE#=VIL : x8 bit). 5. RP# at GND0.2V ensures the lowest power consumption. 6. Command writes involving block erase, (page buffer) program, block lock configuration or OTP program are reliably executed when VPEN=VPENH and VCC=2.7V-3.6V. 7. Refer to Table 5 for valid DIN during a write operation. 8. Never hold OE# low and WE# low at the same timing. 9. Refer to Appendix of LH28F640SP series for more information about query code. 10. STS is VOL when the WSM (Write State Machine) is executing internal block erase, (page buffer) program or OTP program algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with program and page buffer program inactive), (page buffer) program suspend mode, or reset mode.
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Table 5. Command Definitions (10) Command Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend Block Erase and (Page Buffer) Program Resume STS Configuration Set Block Lock Bit Clear Block Lock Bits OTP Program Bus Cycles Req'd 1 2 2 2 1 2 2 4 1 1 2 2 2 2 9 5 5,6 5,7 8 8 4 4 First Bus Cycle Notes Oper(1) Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr(2) X X X X X BA X BA X X X X X X Data(3) FFH 90H 98H 70H 50H 20H 40H or 10H E8H B0H D0H B8H 60H 60H C0H Write Write Write Write X BA X OA CC 01H D0H OD Write Write Write BA WA BA D0H WD N-1 Read Read Read IA or OA QA X ID or OD QD SRD Second Bus Cycle Oper(1) Addr(2) Data(3)
NOTES: 1. Bus operations are defined in Table 4. 2. X=Any valid address within the device. IA=Identifier codes address (Refer to Table 3). QA=Query codes address. Refer to Appendix of LH28F640SP series for details. BA=Address within the block for block erase, page buffer program or set block lock bit. WA=Address of memory location for the Program command. OA=Address of OTP block to be read or programmed (Refer to Figure 3). 3. The upper byte of the data bus (DQ15-DQ8) during command writes is ignored in word mode (BYTE#=VIH : x16 bit). ID=Data to be read from identifier codes. (Refer to Table 3). QD=Data to be read from query database. Refer to Appendix of LH28F640SP series for details. SRD=Data to be read from status register. Refer to Table 7 for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the first edge of CE0, CE1 or CE2 that disables the device or the rising edge of WE# (whichever occurs first) during command write cycles. N-1=N is the number of the words /bytes to be loaded into a page buffer. OD=Data within OTP block. Data is latched on the first edge of CE0, CE1 or CE2 that disables the device or the rising edge of WE# (whichever occurs first) during command write cycles. CC= STS configuration code (Refer to Table 9). 4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code and the data within OTP block (Refer to Table 3). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RP# is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, write the program sequential address and data of "N" times. Finally, write the any valid address within the block to be programmed and the confirm command (D0H).
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Refer to Appendix of LH28F640SP series for details. 8. If both block erase operation and (page buffer) program operation are suspended, the suspended (page buffer) program operation is resumed when writing the Block Erase and (Page Buffer) Program Resume (D0H) command. 9. Following the Clear Block Lock Bits command, all the blocks are unlocked at a time. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
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Table 6. Functions of Block Lock (1), (2) DQ0(3) 0 1 Locked State Name Unlocked Erase/Program Allowed (4) Yes No
NOTES: 1. Selected block is locked by the Set Block Lock Bit command. Following the Clear Block Lock Bits command, all the blocks are unlocked at a time. 2. Locked and unlocked states remain unchanged even after power-up/down and device reset. 3. After writing the Read Identifier Codes/OTP command, read operation outputs the block lock bit status on DQ0 (refer to Table 3). 4. Erase and program are general terms, respectively, to express: block erase and (page buffer) program operations.
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Table 7. Status Register Definition R 15 WSMS 7 R 14 BESS 6 R 13 BECBLS 5 R 12 PBPOPSBLS 4 R 11 VPENS 3 R 10 PBPSS 2 NOTES: R 9 DPS 1 R 8 R 0
SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed
Check SR.7 or STS to determine block erase, (page buffer) program, block lock configuration or OTP program completion. SR.6 - SR.1 are invalid while SR.7="0".
SR.5 = BLOCK ERASE AND CLEAR BLOCK LOCK If both SR.5 and SR.4 are "1"s after a block erase, page buffer program, block lock configuration, STS configuration BITS STATUS (BECBLS) attempt, an improper command sequence was entered. 1 = Error in Block Erase or Clear Block Lock Bits 0 = Successful Block Erase or Clear Block Lock Bits SR.4 = (PAGE BUFFER) PROGRAM, OTP PROGRAM AND SET BLOCK LOCK BIT STATUS (PBPOPSBLS) 1 = Error in (Page Buffer) Program, OTP Program or Set Block Lock Bit 0 = Successful (Page Buffer) Program, OTP Program or Set Block Lock Bit SR.3 = VPEN STATUS (VPENS) 1 = VPEN LOW Detect, Operation Abort 0 = VPEN OK
SR.3 does not provide a continuous indication of VPEN level. The WSM interrogates and indicates the VPEN level only after Block Erase, (Page Buffer) Program, Set Block Lock Bit, Clear Block Lock Bits or OTP Program command sequences. SR.3 is not guaranteed to report accurate feedback SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS when VPENVPENH or VPENLK. (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, (Page Buffer) Program or OTP Program command SR.1 = DEVICE PROTECT STATUS (DPS) sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock 1 = Erase or Program Attempted on a configuration codes after writing the Read Identifier Codes/ Locked Block, Operation Abort OTP command indicates block lock bit status. 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.15 - SR.8 and SR.0 are reserved for future use and should be masked out when polling the status register.
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Table 8. Extended Status Register Definition R 15 SMS 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 R 10 R 2 R 9 R 1 R 8 R 0
XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available
NOTES: After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status XSR.6-0 =RESERVED FOR FUTURE ENHANCEMENTS (R) register.
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Table 9. STS Configuration Definition (1) R 15 R 7 R 14 R 6 R 13 R 5 R 12 R 4 R 11 R 3 R 10 R 2 NOTES: After power-up or device reset, STS configuration is set to "00". DQ1-DQ0 = STS CONFIGURATION CODE (CC) 00 = level mode: RY/BY# indication. (Default) 01 = pulse mode on erase complete. 10 = pulse mode on program complete. 11 = pulse mode on erase or program complete. STS configuration 00 The output of the STS pin is the control signal to prevent accessing a flash memory while the internal WSM is busy (SR.7="0"). R 9 CC 1 R 8 CC 0
DQ15-DQ2 = RESERVED FOR FUTURE ENHANCEMENTS (R)
In STS configuration = "00", STS is VOL when the WSM is STS configuration 01 The output of the STS pin is the control signal to indicate executing internal erase or program algorithms. that the erase operation is completed and the flash memory is available for the next operation. STS configuration codes "01", "10" and "11" are all pulse modes such that the STS pin pulses low then high when the operation indicated by the configuration code is completed. STS configuration 10 The output of the STS pin is the control signal to indicate that the program operation is completed and the flash memory is available for the next operation. STS configuration 11 The output of the STS pin is the control signal to indicate that the erase or program operation is completed and the flash memory is available for the next operation. NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250ns.
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1 Electrical Specifications 1.1 Absolute Maximum Ratings*
Operating Temperature During Read, Erase and Program ...-40C to +85C (1) Storage Temperature During under Bias............................... -40C to +85C During non Bias................................ -65C to +125C Voltage On Any Pin (except VCC, VCCQ and VPEN) ................................................... -0.5V to VCCQ+0.5V (2) VCC and VCCQ Supply Voltage .......... -0.2V to +3.9V (2) VPEN Supply Voltage.......................... -0.2V to +3.9V (2) Output Short Circuit Current ........................... 100mA (3)
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for extended temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC, VCCQ and VPEN pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 3. Output shorted for no more than one second. No more than one output shorted at a time.
1.2 Operating Conditions
Symbol TA VCC VCCQ VPENH Parameter Operating Temperature VCC Supply Voltage I/O Supply Voltage VPEN Voltage Block Erase Cycling: VPEN=VPENH 1, 2 1, 2 1 Notes Min. -40 2.7 2.7 2.7 100,000 Typ. +25 3.0 3.0 3.0 Max. +85 3.6 3.6 3.6 Unit C V V V Cycles Test Conditions Ambient Temperature
NOTES: 1. Refer to DC Characteristics tables for voltage range-specific specification. 2. VCC and VCCQ should be the same voltage.
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1.2.1 Capacitance (1) (TA=+25C, f=1MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Min. Typ. 6 8 Max. 8 12 Unit pF pF Condition VIN=0.0V VOUT=0.0V
NOTE: 1. Sampled, not 100% tested.
1.2.2 AC Input/Output Test Conditions
VCCQ INPUT 0.0 AC test inputs are driven at VCCQ(min) for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns. Worst case speed conditions are when VCC=VCC(min). VCCQ/2 TEST POINTS VCCQ/2 OUTPUT
Figure 4. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
Table 10. Configuration Capacitance Loading Value
VCCQ(min)/2
1N914
Test Configuration VCC=2.7V-3.6V
CL (pF) 30
RL=3.3k DEVICE UNDER TEST CL Includes Jig Capacitances. CL OUT
Figure 5. Transient Equivalent Testing Load Circuit
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1.2.3 DC Characteristics
VCC=2.7V-3.6V Symbol ILI ILO Parameter Input Load Current Output Leakage Current Notes 1 1 Min. -1 -10 Typ. Max. +1 +10 Unit A A Test Conditions VCC=VCCMax., VCCQ=VCCQMax., VIN/VOUT=VCCQ or GND CMOS Inputs, VCC=VCCMax., VCCQ=VCCQMax., Device is disabled (refer to Table 2), RP#=VCCQ0.2V TTL Inputs, VCC=VCCMax., VCCQ=VCCQMax., Device is disabled (refer to Table 2), RP#=VIH CMOS Inputs, VCC=VCCMax., VCCQ=VCCQMax., Device is enabled (refer to Table 2) RP#=GND0.2V IOUT (STS)=0mA CMOS Inputs, VCC=VCCMax., VCCQ=VCCQMax., Device is enabled (refer to Table 2), f=5MHz, IOUT=0mA CMOS Inputs, VCC=VCCMax., VCCQ=VCCQMax., Device is enabled (refer to Table 2), f=33MHz, IOUT=0mA CMOS Inputs, VCC=VCCMax., VCCQ=VCCQMax., Device is enabled (refer to Table 2), f=5MHz, IOUT=0mA CMOS Inputs, VPEN=VPENH TTL Inputs, VPEN=VPENH
50
120
A
ICCS
VCC Standby Current
1, 2, 8
0.71
2
mA
ICCAS
VCC Automatic Power Savings Current 1, 2, 5
50
120
A
ICCD
VCC Reset Current
1
50
120
A
1, 2 Average VCC Page 4 word/ 8 byte Mode Read Current read ICCR 1, 2
15
20
mA
24
29
mA
Average VCC Read 1 word/ 1 byte read Current
1, 2
40
50
mA
ICCW
VCC (Page Buffer) Program, Set Block Lock Bit Current
1, 2, 6 1, 2, 6
35 40
60 70
mA mA
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DC Characteristics (Continued) VCC=2.7V-3.6V Symbol Parameter VCC Block Erase, Clear Block Lock Bits Current VCC (Page Buffer) Program or Block Erase Suspend Current Input Low Voltage Input High Voltage Notes 1, 2, 6 1, 2, 6 1, 3 6 6 -0.5 2.0 Min. Typ. 35 40 Max. 70 80 10 0.8 VCCQ + 0.5 0.4 VOL Output Low Voltage 6, 8 0.2 V Unit mA mA mA V V VCC=VCCMin., VCCQ=VCCQMin., IOL=2mA VCC=VCCMin., VCCQ=VCCQMin., IOL=100A VCC=VCCMin., VCCQ=VCCQMin., IOH=-1.5mA VCC=VCCMin., VCCQ=VCCQMin., IOH=-100A Test Conditions CMOS Inputs, VPEN=VPENH TTL Inputs, VPEN=VPENH Device is disabled (refer to Table 2).
ICCE
ICCWS ICCES VIL VIH
V
0.85x VCCQ VOH Output High Voltage 6, 8 VCCQ -0.2 VPENLK VPEN Lockout Voltage during Normal Operations VPEN Voltage during Block Erase, (Page Buffer) Program, Set Block Lock Bit, Clear Block Lock Bits or OTP Program Operations VCC Lockout Voltage 4, 6, 7 1.0
V
V
V
VPENH VLKO
4, 7
2.7
3.0
3.6
V
4
2.0
V
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V, VCCQ=3.0V and TA=+25C unless VCC is specified. 2. CMOS inputs are either VCCQ0.2V or GND0.2V. TTL inputs are either VIL or VIH. 3. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block erase suspend mode, the device's current draw is the sum of ICCES and ICCR or ICCW. If read is executed while in (page buffer) program suspend mode, the device's current draw is the sum of ICCWS and ICCR. 4. Block erase, (page buffer) program, block lock configuration and OTP program operations are inhibited when VPENVPENLK or VCCVLKO. These operations are not guaranteed outside the specified voltage (VCC=2.7V-3.6V and VPEN=2.7V-3.6V). 5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when addresses are changed. 6. Sampled, not 100% tested. 7. VPEN is not used for power supply pin. With VPENVPENLK, block erase, (page buffer) program, block lock configuration and OTP program operations are inhibited. 8. Includes STS.
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1.2.4 AC Characteristics - Read-Only Operations (1)
TA=-40C to +85C VCC VCCQ Symbol tAVAV tAVQV tELQV tAPA tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tELFL/tELFH tFLQV/tFHQV tFLQZ/tFHQZ Read Cycle Time Address to Output Delay CEX to Output Delay Page Address Access Time OE# to Output Delay RP# High to Output Delay CEX to Output in Low Z OE# to Output in Low Z CEX to Output in High Z OE# to Output in High Z Output Hold from First Occurring Address, CEX or OE# change CEx Setup to BYTE# Going Low or High BYTE# to Output Delay BYTE# to Output in High Z 2 2, 4 2 2, 5 2 2, 5 2, 4 0 10 1000 1000 0 0 35 15 0 10 1000 1000 3 3, 4 Parameter Notes 3.0V-3.6V 3.0V-3.6V Min. 120 120 120 25 25 180 0 0 35 15 Max. 2.7V-3.6V 2.7V-3.6V Min. 120 120 120 30 30 180 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Refer to AC input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. Sampled, not 100% tested. 3. OE# may be delayed up to tELQV tGLQV after the first edge of CE0, CE1 or CE2 that enables the device (refer to Table 2) without impact to tELQV. 4. The timing is defined from the first edge of CE0, CE1 or CE2 that enables the device. 5. The timing is defined from the first edge of CE0, CE1 or CE2 that disables the device.
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A22-0 (A)
VIH VIL
VALID ADDRESS tAVAV tAVQV
Disabled (VIH)
CEX (E)
Enabled (VIL) tELQV tEHQZ tGHQZ
OE# (G)
VIH VIL
WE# (W)
VIH VIL tGLQV tGLQX tELQX tOH VALID OUTPUT tPHQV
DQ15-0 (D/Q)
VOH VOL
High Z
RP# (P)
VIH VIL tELFL/tELFH tFLQV/tFHQV tFLQZ/tFHQZ
BYTE# (F)
VIH VIL
Figure 6. AC Waveform for 1-Word/ 1-Byte Read Operations (Status Register, Identifier Codes, OTP Block or Query Code) NOTE: 1. Status register, identifier codes, OTP block and query code can only be read in 1-word/ 1-byte read operations.
Rev. 0.06
LHF64P01
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A22-3 (A)
VIH VIL tAVQV VIH VIL
VALID ADDRESS
A2-1 (A)
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
Disabled (VIH)
CEX (E)
Enabled (VIL) tELQV tEHQZ tGHQZ
OE# (G)
VIH VIL
WE# (W)
VIH VIL tGLQX tELQX tAPA tOH tGLQV
DQ15-0 (D/Q)
VOH VOL
High Z
tPHQV
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
RP# (P)
VIH VIL tELFH tFHQV tFHQZ VIH VIL
BYTE# (F)
Figure 7. AC Waveform for 4-Word Page Mode Read Operations (Memory Array) NOTE: 1. Memory array supports page mode read operations.
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A22-3 (A)
VIH VIL tAVQV VIH VIL
VALID ADDRESS
A2-0 (A)
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
Disabled (VIH)
CEX (E)
Enabled (VIL) tELQV
tEHQZ tGHQZ
OE# (G)
VIH VIL
WE# (W)
VIH VIL tGLQX tELQX
tGLQV tAPA tOH
DQ7-0 (D/Q)
VOH VOL
High Z
tPHQV
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
RP# (P)
VIH VIL tELFL tFLQV tFLQZ VIH VIL
BYTE# (F)
Figure 8. AC Waveform for 8-Byte Page Mode Read Operations (Memory Array) NOTE: 1. Memory array supports page mode read operations.
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1.2.5 AC Characteristics - Write Operations (1), (2)
VCC=2.7V-3.6V, TA=-40C to +85C Symbol tAVAV tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tVVWH (tVVEH) tWHGL (tEHGL) tWHR0 (tEHR0) tWHRL (tEHRL) tQVVL tFLWH/tFHWH (tFLEH/tFHEH) tWHFL/tWHFH (tEHFL/tEHFH) Write Cycle Time RP# High Recovery to WE# (CEX) Going Low CEX (WE#) Setup to WE# (CEX) Going Low WE# (CEX) Pulse Width Low Data Setup to WE# (CEX) Going High Address Setup to WE# (CEX) Going High CEX (WE#) Hold from WE# (CEX) High Data Hold from WE# (CEX) High Address Hold from WE# (CEX) High WE# (CEX) Pulse Width High VPEN Setup to WE# (CEX) Going High Write Recovery before Read WE# (CEX) High to SR.7 Going "0", STS Going Low VPEN Hold from Valid SRD, STS High Z BYTE# Setup to WE# (CEX) Going High BYTE# Hold from WE# (CEX) High 3, 9 9 4, 9, 10 7, 10 7, 10 10 10 10 5, 9, 10 3, 10 8 10, 11 3, 6, 11 10 10 0 50 90 Parameter Notes Min. 120 1 0 70 50 55 0 0 0 30 0 35 500 Max. Unit ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. The timing characteristics for reading the status register during block erase, (page buffer) program, block lock configuration and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. A write operation can be initiated and terminated with either CE0, CE1, CE2 or WE#. 3. Sampled, not 100% tested. 4. Write pulse width low (tWP) is defined from the first edge of CE0, CE1 or CE2 that enables the device or the falling edge of WE# (whichever occurs last) to the first edge of CE0, CE1 or CE2 that disables the device or the rising edge of WE# (whichever occurs first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH. 5. Write pulse width high (tWPH) is defined from the first edge of CE0, CE1 or CE2 that disables the device or the rising edge of WE# (whichever occurs first) to the first edge of CE0, CE1 or CE2 that enables the device or the falling edge of WE# (whichever occurs last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. 6. VPEN should be held at VPEN=VPENH until determination of block erase, (page buffer) program, block lock configuration or OTP program success (SR.1/3/4/5=0). 7. Refer to Table 5 for valid address and data for block erase, (page buffer) program, block lock configuration and OTP program. 8. The output delay time tAVQV or tELQV is required in addition to tWHGL (tEHGL) for read operations after command writes. 9. The timing is defined from the first edge of CE0, CE1 or CE2 that enables the device. 10. The timing is defined from the first edge of CE0, CE1 or CE2 that disables the device. 11. STS timings depend on STS configuration.
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LHF64P01
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NOTE 1 A22-0 (A)
VIH VIL
NOTE 2
VALID ADDRESS tAVAV
NOTE 3
VALID ADDRESS tAVWH (tAVEH) tWHAX (tEHAX) VALID ADDRESS
Disabled (VIH)
CEX (E)
Enabled (VIL) tELWL (tWLEL) tWHEH (tEHWH)
NOTES 5, 6
tWHGL (tEHGL)
OE# (G)
VIH VIL tPHWL (tPHEL) VIH VIL tWLWH (tELEH ) tWHDX (tEHDX) tDVWH (tDVEH) tWHQV1,2,3,4,5,6 (tEHQV1,2,3,4,5,6) tWHWL (tEHEL)
NOTES 5, 6
WE# (W)
DQ15-0 (D/Q)
VIH VIL DATA IN DATA IN tWHRL (tEHRL) (tWHR0 (tEHR0))
VALID SRD
High Z
STS ("1") (R) (SR.7) VOL
("0")
NOTE 4
RP# (P)
VIH VIL tFLWH/tFHWH (tFLEH/tFHEH) tWHFL/tWHFH (tEHFL/tEHFH)
BYTE# (F)
VIH VIL tVVWH (tVVEH) tQVVL
VPENH
VPEN (V)
VPENLK VIL
NOTES: 1. VCC power-up and standby. 2. Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. This waveform illustrates the case when STS is in level mode (RY/BY#). 5. Read status register data. 6. For read operation, OE# and CEX must be driven active, and WE# de-asserted.
Figure 9. AC Waveform for Write Operations
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LHF64P01
26
1.2.6 Reset Operations
tPHQV RP#
(P)
VIH VIL tPLPH
High Z
VALID OUTPUT
DQ15-0 (D/Q)
VOH VOL
(A) Reset during Read Array Mode
ABORT COMPLETE
SR.7="1"
tPLRH RP#
(P)
tPHQV
VIH VIL tPLPH
High Z
VALID OUTPUT
DQ15-0 (D/Q)
VOH VOL
(B) Reset during Erase or Program Mode
VCC
VCC(min) GND t2VPH tVHQV tPHQV
RP#
(P)
VIH VIL
DQ15-0 (D/Q)
VOH VOL
High Z
VALID OUTPUT
(C) RP# rising timing
Figure 10. AC Waveform for Reset Operations Reset AC Specifications (VCC=2.7V-3.6V, TA=-40C to +85C)
Symbol tPLPH tPLRH t2VPH tVHQV
Parameter RP# Low to Reset during Read (RP# must be low during power-up.) RP# Low to Reset during Erase or Program VCC 2.7V to RP# High VCC 2.7V to Output Delay
Notes 1, 2, 3 1, 3, 4 1, 3, 5 3
Min. 100
Max.
Unit ns
30 100 1
s ns ms
NOTES: 1. A reset time, tPHQV, is required from the later of SR.7 (STS) going "1" (High Z) or RP# going high until outputs are valid. Refer to AC Characteristics - Read-Only Operations for tPHQV. 2. The device may reset if tPLPH is <100ns, but this is not guaranteed. 3. Sampled, not 100% tested. 4. If RP# asserted while a block erase, (page buffer) program, block lock configuration or OTP program operation is not executing, the reset will complete within 100ns. 5. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range and also has been in stable there.
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1.2.7 Block Erase, (Page Buffer) Program and Block Lock Configuration Performance(3)
VCC=2.7V-3.6V, TA=-40C to +85C Symbol Parameter Page Buffer Program Time (Time to Program 16 words/ 32 bytes) tWHQV3/ tEHQV3 Program Time Block Program Time (Using Page Buffer Program Command) tWHQV4/ tEHQV4 tWHQV5/ tEHQV5 tWHQV6/ tEHQV6 tWHRH1/ tEHRH1 tWHRH2/ tEHRH2 tERES Block Erase Time Set Block Lock Bit Time Clear Block Lock Bits Time (Page Buffer) Program Suspend Latency Time to Read Block Erase Suspend Latency Time to Read Latency Time from Block Erase Resume Command to Block Erase Suspend Command Notes 2, 6, 7 2 2 2 2 2 4 4 VPEN=VPENH Min. Typ.(1) 400 210 1.6 1 64 0.5 25 26 Max. 1200 630 4.8 5 85 0.7 90 40 Unit s s s s s s s s s
5
600
NOTES: 1. Typical values measured at VCC=3.0V, VPEN=3.0V and TA=+25C. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. 4. A latency time is required from writing suspend command (the first edge of CE0, CE1 or CE2 that disables the device or the rising edge of WE#) until SR.7 going "1" or STS going High Z. 5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished. 6. These values are valid when the page buffer is full, and the start address is aligned on a 16-word/ 32-byte boundary. 7. Program time per byte (tWHQV1/ tEHQV1) is 12.5s/byte (typical). Program time per word (tWHQV2/ tEHQV2) is 25.0s/word (typical).
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LHF64P01
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2 Related Document Information(1)
Document No. FUM03201 NOTE: 1. International customers should contact their local SHARP or distribution sales offices. Document Name LH28F640SP series Appendix
Rev. 0.06
i
LH28F640SPXX-XXXXX Flash MEMORY ERRATA
1. Table 5. Command Definitions
PROBLEM While block erase or (page buffer) program is being suspended by issuing Block Erase and (Page Buffer) Program Suspend command, memory array data can not be normally read by issuing read array command. WORKAROUND Block Erase and (Page Buffer) Program Suspend command should not be issued. STATUS This is intended to be fixed in future devices.
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i
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VCC VCCQ
VCC(min) GND VIH tVR t2VPH tPHQV
RP# (P) (RST#) VPEN *1 (V) (VPP) ADDRESS (A)
VIL VPENH (VPPH) GND tR or tF VIH VIL tF tAVQV Valid Address tELQV tR tR or tF
Disabled (VIH)
CEX
(E)
Enabled (VIL)
VIH WE# (W) VIL tF VIH OE#
(G)
tGLQV
tR
VIL
DATA
(D/Q)
VOH VOL
High Z
Valid Output
*1 To prevent the unwanted writes, system designers should consider the design, which applies VPEN (VPP) to 0V during read operations and VPENH (VPPH) during write or erase operations. See the application note AP-007-SW-E for details.
Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.
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A-1.1.1 Rise and Fall Time
Symbol tVR tR tF VCC Rise Time
Parameter
Notes 1 1, 2 1, 2
Min. 0.5
Max. 30000 1 1
Unit s/V s/V s/V
Input Signal Rise Time Input Signal Fall Time
NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations.
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A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal VIH (Min.)
Input Signal VIH (Min.)
VIL (Max.) Input Signal
VIL (Max.) Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.).
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A-2 RELATED DOCUMENT INFORMATION(1)
Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E
Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, VPP Electric Potential Switching Circuit
NOTE: 1. International customers should contact their local SHARP or distribution sales office.
030313

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